/****************************************************************************** 
 * LPC24xx Standard Peripheral Library
 * Version: 1.0.0
 * 
 *  Copyright (C) 2012  Timothy Gack
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 3 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software Foundation,
 * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301  USA 
 *******************************************************************************
 * System Control Block
 *
 * The System Control Block includes several system features and control registers
 * for a number of functions that are not related to specific peripheral devises.
 * These include:
 *
 * - Reset
 * - Brown-Out Detection
 * - External Interrupt Inputs
 * - Miscellaneous System Controls and Status
 * - Code Security vs. Debugging
 *
 * Each type of function has its own register(s) if any are required and 
 * unneeded bits are defined as reserved in order to allow future expansion.
 *******************************************************************************/
#ifndef _LPC24XX_SYSTEM_CONTROL_H_
#define _LPC24XX_SYSTEM_CONTROL_H_



#include "lpc24xx_std_includes.h"

#ifdef __cplusplus
extern "C" {
#endif

typedef enum _INTERRUPT_MODE_
{
  EXTINT_MODE_LEVEL = 0,
  EXTINT_MODE_EDGE = 1
}INTERRUPT_MODE;

typedef enum _INTERRUPT_POLARITY_
{
  EXTINT_POLARITY_LOW_FALLING = 0,
  EXTINT_POLARITY_HIGH_RISING = 1
}INTERRUPT_POLARITY;

typedef enum _AHB_SCHEDULE_
{
  SCHEDULE_PRIORITY = 0,
  SCHEDULE_UNIFORM = 1
}AHB_SCHEDULE;

typedef enum _AHB_BREAK_BURSRT_
{
  BREAK_ALL_BURSTS = 0,
  BREAK_ALL_BURST_GREATER_4,
  BREAK_ALL_BURST_GREATER_8,
  BREAK_BURST_NEVER
}AHB_BREAK_BURSRT;

typedef enum _AHB_QUANTUM_TYPE_
{
  QUANTUM_CLOCK = 0,
  QUANTUM_CYCLE
}AHB_QUANTUM_TYPE;

typedef enum _AHB_QUANTUM_SIZE_
{
  PREMPTIVE_1AHB_QUANTUM = 0,
  PREMPTIVE_2AHB_QUANTA,
  PREMPTIVE_4AHB_QUANTA,
  PREMPTIVE_8AHB_QUANTA,
  PREMPTIVE_16AHB_QUANTA,
  PREMPTIVE_32AHB_QUANTA,
  PREMPTIVE_64AHB_QUANTA,
  PREMPTIVE_128AHB_QUANTA,
  PREMPTIVE_256AHB_QUANTA,
  PREMPTIVE_512AHB_QUANTA,
  PREMPTIVE_1024AHB_QUANTA,
  PREMPTIVE_2048AHB_QUANTA,
  PREMPTIVE_4096AHB_QUANTA,
  PREMPTIVE_8192AHB_QUANTA,
  PREMPTIVE_16384AHB_QUANTA,
  NON_PREMPTIVE_INFINITE_AHB_QUANTA
}AHB_QUANTUM_SIZE;

typedef enum _GPIOM_
{
  GPIOM_LEGACY = 0,
  GPIOM_FASTIO = 1
}GPIOM;


typedef enum _EMC_RESET_DISABLE_
{
  EMC_RESET_ANY = 0,
  EMC_RESET_POR_BRN = 1
}EMC_RESET_DISABLE;

typedef enum _EMC_BURST_CONTROL_
{
  BURST_ENABLE = 0,
  BURST_DISABLE = 1
}EMC_BURST_CONTROL;

typedef enum _MCI_POWER_ACTIVE_LEVEL_
{
  MCIPWR_LOW = 0,
  MCIPWR_HIGH = 1
}MCI_POWER_ACTIVE_LEVEL;

typedef enum _OSCEN_
{
  OSCEN_DISABLED = 0,
  OSCEN_ENABLED = 1
}OSCEN;

typedef enum _OSCSTAT_
{
  OSCSTAT_NOT_READY = 0,
  OSCSTAT_READY = 1
}OSCSTAT;

typedef enum _OSCRANGE_
{
  OSCRANGE_1MHZ_20MHZ = 0,
  OSCRANGE_15MHZ_25MHZ = 1
}OSCRANGE;

typedef enum _CLOCKSOURCE_
{
  CLOCKSOURCE_INTERNAL_RC = 0,
  CLOCKSOURCE_MAIN,
  CLOCKSOURCE_RTC
}CLOCKSOURCE;

typedef enum _CLKDIV_
{
  CLKDIV_4=0,
  CLKDIV_1=1,     // Note: never set PCLK_RTC to divide by 1
  CLKDIV_2=2,
  CLKDIV_8=3,
  CLKDIV_6=3      // Note: CAN1, CAN2, and CAN filtering only
}CLKDIV;

typedef union _EXTINT_TYPE_
{
  uint8_t value;
  struct _EXTINT_TYPE_BITFIELDS_
  {
    unsigned eint0 : 1;
    unsigned eint1 : 1;
    unsigned eint2 : 1;
    unsigned eint3 : 1;
    unsigned reserved : 4;
  }bits;
}EXTINT_TYPE, *LP_EXTINT_TYPE;


typedef union _INTWAKE_TYPE_
{
  uint16_t value;
  struct _INTWAKE_TYPE_BITFIELDS_
  {
    unsigned extwake0 : 1;
    unsigned extwake1 : 1;
    unsigned extwake2 : 1;
    unsigned extwake3 : 1;
    unsigned ethwake : 1;
    unsigned usbwake : 1;
    unsigned canwake : 1;
    unsigned gpio0wake : 1;
    unsigned gpio2wake : 1;
    unsigned reserved0 : 5;
    unsigned bodwake : 1;
    unsigned rtcwake : 1;
  }bits;
}INTWAKE_TYPE, *LP_INTWAKE_TYPE;

typedef union _EXTMODE_TYPE_
{
  uint8_t value;
  struct _EXTMODE_TYPE_BITFIELDS_
  {
    unsigned extmode0 : 1;
    unsigned extmode1 : 1;
    unsigned extmode2 : 1;
    unsigned extmode3 : 1;
    unsigned reserved : 4;
  }bits;
}EXTMODE_TYPE, *LP_EXTMODE_TYPE;

typedef union _EXTPOLAR_TYPE_
{
  uint8_t value;
  struct _EXTPOLAR_TYPE_BITFIELDS_
  {
    unsigned extpolar0 : 1;
    unsigned extpolar1 : 1;
    unsigned extpolar2 : 1;
    unsigned extpolar3 : 1;
    unsigned reserved : 4;
  }bits;
}EXTPOLAR_TYPE, *LP_EXTPOLAR_TYPE;

typedef union _RSID_TYPE_
{
  uint8_t value;
  struct _RSID_TYPE_BITFIELDS_
  {
    unsigned por : 1;     // Power On Reset signal
    unsigned extr : 1;    // External Reset signal
    unsigned wdtr : 1;    // Watchdog Timer reset signal
    unsigned bodr : 1;    // Brownout detect signal
    unsigned reserved : 4;
  }bits;
}RSID_TYPE, *LP_RSID_TYPE;


typedef union _AHBCFG1_TYPE_
{
  uint32_t value;
  struct _AHBCFG1_TYPE_BITFIELDS_
  {
    unsigned scheduler : 1;
    unsigned break_burst : 2;
    unsigned quantum_type : 1;
    unsigned quantum_size : 4;
    unsigned default_master : 3;
    unsigned reserved0 : 1;
    unsigned ep1 : 3;
    unsigned reserved1 : 1;
    unsigned ep2 : 3;
    unsigned reserved2 : 1;
    unsigned ep3 : 3;
    unsigned reserved3 : 1;
    unsigned ep4 : 3;
    unsigned reserved4 : 1;
    unsigned ep5 : 3;
    unsigned reserved5 : 1;
  }bits;
}AHBCFG1_TYPE, *LP_AHBCFG1_TYPE;

typedef union _AHBCFG2_TYPE_
{
  uint32_t value;
  struct _AHBCFG2_TYPE_BITFIELDS_
  {
    unsigned scheduler : 1;
    unsigned break_burst : 2;
    unsigned quantum_type : 1;
    unsigned quantum_size : 4;
    unsigned default_master : 2;
    unsigned reserved0 : 1;
    unsigned ep1 : 3;
    unsigned reserved1 : 1;
    unsigned ep2 : 3;
    unsigned reserved2 : 1;
    unsigned ep3 : 3;
    unsigned reserved3 : 1;
    unsigned ep4 : 3;
    unsigned reserved4 : 1;
    unsigned ep5 : 3;
    unsigned reserved5 : 1;
  }bits;
}AHBCFG2_TYPE, *LP_AHBCFG2_TYPE;

typedef union _SCS_TYPE_
{
  uint32_t value;
  struct _SCS_TYPE_BITFIELDS_
  {
    unsigned gpiom : 1;
    unsigned emcResetDisable : 1;
    unsigned emcBurstCtrl : 1;
    unsigned mcipwrActiveLevel : 1;
    unsigned oscRange : 1;
    unsigned oscen : 1;
    unsigned oscstat : 1;
    unsigned reserved : 25;
  }bits;
}SCS_TYPE, *LP_SCS_TYPE;

typedef union _MEMMAP_TYPE_
{
  uint8_t value;
  struct _MEMMEP_TYPE_BITFIELDS_
  {
    unsigned map : 2;
    unsigned reserved : 6;
  }bits;
}MEMMAP_TYPE, *LP_MEMMAP_TYPE;

typedef union _CLKSRCSEL_TYPE_
{
  uint8_t value;
  struct _CLKSRCSEL_TYPE_BITFIELDS_
  {
    unsigned clksrc : 2;
    unsigned reserved : 6;
  }bits;
}CLKSRCSEL_TYPE, *LP_CLKSRCSEL_TYPE;

typedef union _PLLCON_TYPE_
{
  uint8_t value;
  struct _PLLCON_TYPE_BITFIELDS_
  {
    unsigned plle : 1;
    unsigned pllc : 1;
    unsigned reserved : 6;
  }bits;
}PLLCON_TYPE, *LP_PLLCON_TYPE;

typedef union _PLLCFG_TYPE_
{
  uint32_t value;
  struct _PLLCFG_TYPE_BITFIELDS_
  {
    unsigned msel : 15;
    unsigned reserved0 : 1;
    unsigned nsel : 8;
    unsigned reserved : 8;
  }bits;
}PLLCFG_TYPE, *LP_PLLCFG_TYPE_;

typedef union _PLLSTAT_TYPE_
{
  uint32_t value;
  struct _PLLSTAT_TYPE_BITFIELDS_
  {
    unsigned msel : 15;
    unsigned reserved0 : 1;
    unsigned nsel : 8;
    unsigned plle : 1;
    unsigned pllc : 1;
    unsigned plock: 1;
    unsigned reserved1 : 5;
  }bits;
}PLLSTAT_TYPE, *LP_PLLSTAT_TYPE;


typedef union _PLLFEED_TYPE_
{
  uint8_t value;
}PLLFEED_TYPE, *LP_PLLFEED_TYPE;

typedef union _CCLKCFG_TYPE_
{
  uint8_t value;
}CCLKCFG_TYPE, *LP_CCLKCFG_TYPE;

typedef union _USBCLKCFG_TYPE_
{
  uint8_t value;
}USBCLKCFG_TYPE, *LP_USBCLKCFG_TYPE;

typedef union _IRCTRIM_TYPE_
{
  uint16_t value;
  struct _IRCTRIM_TYPE_BITFIELDS_
  {
    unsigned irctrim : 8;
    unsigned reserved : 8;
  }bits;
}IRCTRIM_TYPE, *LP_IRCTRIM_TYPE;

typedef union _PCLKSEL0_TYPE_
{
  uint32_t value;
  struct _PCLKSEL0_TYPE_BITFIELDS_
  {
    unsigned pclk_wdt : 2;
    unsigned pclk_timer0 : 2;
    unsigned pclk_timer1 : 2;
    unsigned pclk_uart0 : 2;
    unsigned pclk_uart1 : 2;
    unsigned pclk_pwm0 : 2;
    unsigned pclk_pwm1 : 2;
    unsigned pclk_i2c0 : 2;
    unsigned pclk_spi : 2;
    unsigned pclk_rtc : 2;
    unsigned pclk_ssp1 : 2;
    unsigned pclk_dac : 2;
    unsigned pclk_adc : 2;
    unsigned pclk_can1 : 2;
    unsigned pclk_can2 : 2;
    unsigned pclk_acf : 2;
  }bits;
}PCLKSEL0_TYPE, *LP_PCLKSEL0_TYPE;


typedef union _PCLKSEL1_TYPE_
{
  uint32_t value;
  struct _PCLKSEL1_TYPE_BITFIELDS_
  {
    unsigned pclk_bat_ram : 2;
    unsigned pclk_gpio : 2;
    unsigned pclk_pcb : 2;
    unsigned pclk_i2c1 : 2;
    unsigned pclk_reserved0 : 2;
    unsigned pclk_ssp0 : 2;
    unsigned pclk_timer2 : 2;
    unsigned pclk_timer3 : 2;
    unsigned pclk_uart2 : 2;
    unsigned pclk_uart3 : 2;
    unsigned pclk_i2c2 : 2;
    unsigned pclk_i2s : 2;
    unsigned pclk_mci : 2;
    unsigned pclk_reserved1 : 2;
    unsigned pclk_syscon : 2;
    unsigned pclk_reserved2 : 2;
  }bits;
}PCLKSEL1_TYPE, *LP_PCLKSEL1_TYPE;


typedef union _PCON_TYPE_
{
  uint8_t value;
  struct _PCON_TYPE_BITFIELDS_
  {
    unsigned pm0 : 1;
    unsigned pm1 : 1;
    unsigned bodpdm : 1;
    unsigned bogd : 1;
    unsigned bord : 1;
    unsigned reserved : 2;
    unsigned pm2 : 1;
  }bits;
}PCON_TYPE, *LP_PCON_TYPE;

typedef union _PCONP_TYPE_
{
  uint32_t value;
  struct _PCONP_TYPE_BITFIELDS_
  {
    unsigned reserved0 : 1;
    unsigned pctim0 : 1;
    unsigned pctim1 : 1;
    unsigned pcuart0 : 1;
    unsigned pcuart1 : 1;
    unsigned pcpwm0 : 1;
    unsigned pcpwm1 : 1;
    unsigned pci2c0 : 1;
    unsigned pcspi : 1;
    unsigned pcrtc : 1;
    unsigned pcssp1 : 1;
    unsigned pcemc : 1;
    unsigned pcad : 1;
    unsigned pccan1 : 1;
    unsigned pccan2 : 1;
    unsigned reserved1 : 4;
    unsigned pci2c1 : 1;
    unsigned pclcd : 1;
    unsigned pcssp0 : 1;
    unsigned pctim2 : 1;
    unsigned pctim3 : 1;
    unsigned pcuart2 : 1;
    unsigned pcuart3 : 1;
    unsigned pci2c2 : 1;
    unsigned pci2s : 1;
    unsigned pcsdc : 1;
    unsigned pcgpdma : 1;
    unsigned pcenet : 1;
    unsigned pcusb : 1;
  }bits;
}PCONP_TYPE, *LP_PCONP_TYPE;


#define EXTINT    (*(volatile EXTINT_TYPE *)(SCB_BASE_ADDR + 0x140))
#define INTWAKE   (*(volatile INTWAKE_TYPE *)(SCB_BASE_ADDR + 0x144))

#define EXTMODE   (*(volatile EXTMODE_TYPE *)(SCB_BASE_ADDR + 0x148))
#define EXTPOLAR  (*(volatile EXTPOLAR_TYPE *)(SCB_BASE_ADDR + 0x14C))
#define RSID      (*(volatile RSID_TYPE *)(SCB_BASE_ADDR + 0x180))

#define AHBCFG1   (*(volatile AHBCFG1_TYPE *)(SCB_BASE_ADDR + 0x188))
#define AHBCFG2   (*(volatile AHBCFG2_TYPE *)(SCB_BASE_ADDR + 0x18C))

#define SCS       (*(volatile SCS_TYPE *)(SCB_BASE_ADDR + 0x1A0))
#define MEMMAP    (*(volatile MEMMAP_TYPE *)(SCB_BASE_ADDR + 0x040))
#define CLKSRCSEL (*(volatile CLKSRCSEL_TYPE *)(SCB_BASE_ADDR + 0x10C))

#define PLLCON    (*(volatile PLLCON_TYPE *)(SCB_BASE_ADDR + 0x080))
#define PLLCFG    (*(volatile PLLCFG_TYPE *)(SCB_BASE_ADDR + 0x084))
#define PLLSTAT   (*(volatile PLLSTAT_TYPE *)(SCB_BASE_ADDR + 0x088))
#define PLLFEED   (*(volatile PLLFEED_TYPE *)(SCB_BASE_ADDR + 0x08C))

#define CCLKCFG   (*(volatile CCLKCFG_TYPE *)(SCB_BASE_ADDR + 0x104))
#define USBCLKCFG (*(volatile USBCLKCFG_TYPE *)(SCB_BASE_ADDR + 0x108))

#define IRCTRIM   (*(volatile IRCTRIM_TYPE *)(SCB_BASE_ADDR + 0x1A4))

#define PCLKSEL0  (*(volatile PCLKSEL0_TYPE *)(SCB_BASE_ADDR + 0x1A8))
#define PCLKSEL1  (*(volatile PCLKSEL1_TYPE *)(SCB_BASE_ADDR + 0x1AC))

#define PCON      (*(volatile PCON_TYPE *)(SCB_BASE_ADDR + 0x0C0))
#define PCONP     (*(volatile PCONP_TYPE *)(SCB_BASE_ADDR + 0x0C4))


#ifdef __cplusplus
}
#endif

#endif
